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LOW-TEMPERATURE CRYSTALLIZATION OF AMORPHOUS SILICON THIN FILMS ON BOTTOM GATE ELECTRODES BY USING YSZ CRYSTALLIZATION-INDUCTION LAYER AND SOLID-PHASE CRYSTALLIZATION METHODS
Corresponding Author(s) : Mai Thi Kieu Lien
UED Journal of Social Sciences, Humanities and Education,
Vol. 6 No. 3 (2016): UED JOURNAL OF SOCIAL SCIENCES, HUMANITIES AND EDUCATION
Abstract
We have successfully crystallized amorphous silicon (a-Si) thin films at a low temperature by using the crystallization-induction layer of yttria stabilized zirconia (YSZ) in combination with solid-phase crystallization (SPC) methods. The obtained polycrystalline silicon (poly-Si) thin films via these methods can be implemented in TFTs fabrication. The capability of using the YSZ layer as an insulation gate was also investigated by means of electrical property measurements like the dependence of capacity on voltage (C-V), and the dependence of eclectric current power on voltage (I-V). The C-V measurement showed that interface properties between the YSZ layer and the crystallized Si film were relatively good. Moreover, hysteresis loops were hardly observed. The I-V measurement showed a relatively low leakage current. This means that the YSZ layer can operate reliably as a comparatively good insulator.
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